1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, which can improve performances of the semiconductor device.
2. Discussion of the Related Art
An MOS(Metal Oxide Semiconductor Structure), in which a silicon oxide film having a good insulating property is formed on a surface of a silicon before forming electrodes thereon, brings about innovated improvement in performance and fabrication of transistors. In the MOS, there are pMOS(p channel MOS), nMOS(n channel MOS) and CMOS. Though pMOS devices are used mostly initially which has a low power consumption and relatively easy process control in fabrication of an integrated device, nMOS devices became popular as a device speed is regarded important since a mobility of an electron is about 2.5 time higher than a mobility of a hole. As the CMOS device is featured in its low power consumption despite of its complicacy in view of a packing density and fabrication process compared to pMOS or nMOS devices, the nMOS is used in a memory of a semiconductor device while the CMOS is used in the periphery. For a higher device packing density and faster operation, a size of the MOS device, particularly, a length of channel has been reduced. As a result, since, as a generally used power, 5 v is applied as before though a distance between source and drain regions is reduced, a field intensity in the MOS device is increased as much. As the channel length is shortened further for a higher density device packing, a carrier, obtaining high energy from the above field during the carrier flows from the source to channel and obtaining a temperature significantly higher than a lattice around it when it reaches to the drain already, causes impact ionization. Since electrons are more susceptible to the impact ionization than holes, it causes a greater problem in the nMOS device rather than in the nMOS device. Of pairs of electrons and holes produced from such a carrier impact, while the electrons are attracted toward a drain, an n type impurity region in case of the nMOS device, the holes flow toward a substrate, a p type impurity doped region, which flow of holes forms a substrate current. And, since a portion of holes also flow toward the source, biasing a pn junction in a orderly direction and causing a more flow of current by action of an npn transistor, the impact ionization is occurred the more, which increases the drain current the more. At the end, the carriers in the channel is accelerated to have an energy higher than a barrier between the substrate and the gate oxide by a strong field around the drain, to become hot electrons(thermal electrons) and to be injected into the gate oxide film. The injected electrons are called "channel hot electrons". The electrons or holes injected thus into the gate oxide film are trapped in the gate oxide film and produces an energy level at an interface between the substrate and the gate oxide film, thereby causing problems of a changed threshold voltage or a dropped mutual conductance. The aforementioned phenomena, called hot carrier effects, is caused by a strong field generated in a pinch off region near the drain. In order to improve such problems, an MOS transistor of an LDD(Lightly Doped Drain) is suggested, in which a low concentration layer with a moderate impurity concentration profile is formed between the drain and the channel, for reducing the strong field and improving the hot carrier effects.
An LDD structure has a self-aligned lightly doped impurity region(LDD region) between the channel region and heavily doped impurity regions(source/drain regions) on both sides of the channel region. This LDD region spread out the strong field near a drain junction, preventing the rapid acceleration of the carriers from the source even under a high applied voltage, thereby solving the unstableness of current caused by the hot carrier. However, as the LDD region has a low concentration(about 1/1000) in comparison to a heavy concentration of the source/drain regions, a resistance in the region acts as a parasitic resistance, that reduces a driving current. In conclusion, if the concentration of the LDD region is increased, a substrate current is increased increasing the hot carrier effect, if the concentration is decreased, the driving current is decreased due to the parasitic resistance. Therefore, the concentration in the LDD region should be easy to control and set to be high as far as possible. One of methods meeting the above requirement which is used widely is a method in which LDD regions are formed on both sides of a gate electrode by injecting ions using the gate electrode as mask, sidewall spacers of oxide are formed at sides of the gate electrode, and ion are injected using the sidewall spacers and the gate electrode, to form the heavily doped source/drain regions. An MOS transistor of LDD formed in the aforementioned method has lightly doped regions not only in the drain region, but also in the source region. Besides, there is an MOSFET device which prevents the punch through by forming a pocket region in a form bounding the lightly doped regions of source/drain at a portion deep near the channel started both from the source/drain regions toward the channel.
A background art method for fabricating an MOS transistor in a semiconductor device will be explained with reference to the attached drawings. FIGS. 1a.about.1g illustrates sections showing the steps of a background art method for fabricating an MOS transistor in a semiconductor device.
Referring to FIG. 1a, a well region 2 is formed using a generally used process in a semiconductor substrate 1. As shown in FIG. 1b, an isolation region(field regions) is defined, and an isolation film 3 is formed on the semiconductor substrate 1 in the isolation region. As shown in FIG. 1c, channel ions are injected under a surface of the well region 2 in the semiconductor substrate 1 for adjusting a threshold voltage V.sub.T. As shown in FIG. 1d, a gate oxide film 4 is formed on an entire surface of the isolating film 3 inclusive of the semiconductor substrate 1. As shown in FIG. 1e, a gate electrode 5 is formed on the gate oxide film 4. There are a refractory metal film 6 and a cap gate oxide film 7 over the gate electrode 5. The gate electrode 5 has a width becoming the narrower as the semiconductor device is packed the higher. As shown in FIG. 1f, the gate electrode 5 is used as a mask in lightly doping portions of the well regions 2 on both sides of the gate electrode 5 with impurities of a conductivity opposite to a conductivity of the well region 2, to form LDD regions 8. Then, sidewall spacers 9 are formed at sides of the cap gate oxide film 7, the refractory metal film 6 and the gate electrode 5. A portion of the well region 2 between the LDD regions 8 is a channel region 10. As shown in FIG. 1g, the gate electrode 5 and the sidewall spacers 9 are used as masks in heavily doping portions of the well region 3 on both sides of the sidewall spacers 9 with impurities of a conductivity opposite to a conductivity of the well region 3, to form source/drain regions 11.
However, the background art method for fabricating an MOS transistor in a semiconductor device has the following problems.
First, the incapability of preventing occurrence of a leakage current from source/drain regions to the well region due to the source/drain regions formed in direct contact with the well region degrades a reliability as a transistor in a semiconductor device.
Second, the generation of parasitic capacitance at an interface of the well region and the source/drain regions due to a difference of dopants drops a driving speed of the transistor.
Third, the incapability of prevention of punch through between a substrate bulk under the channel region and the source/drain regions as a length of the channel is shortened in proportion to the advance of device integration causes problems, such as degradation of memory.
Fourth, the depth of doping could not be controlled perfectly in the doping of the source/drain regions.